Fundamentals of VHDL for FPGA Programming Using Vivado
Fundamentals of VHDL for FPGA Programming Using Vivado
Majid Pakdel received his Master's degree in electrical power engineering from Isfahan University of Technology, Iran, in 2007, his PhD in Electrical Power Engineering from University of Zanjan in 2018, and his second Masters degree in computer engineering-Artificial Intelligence and Robotics from Malek Ashlar University of Technology, Tehran, in 2023. He has published over 20 papers and books in the fields of electrical engineering and computer science.
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Majid Pakdel received his Master's degree in electrical power engineering from Isfahan University of Technology, Iran, in 2007, his PhD in Electrical Power Engineering from University of Zanjan in 2018, and his second Masters degree in computer engineering-Artificial Intelligence and Robotics from Malek Ashlar University of Technology, Tehran, in 2023. He has published over 20 papers and books in the fields of electrical engineering and computer science.
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